Architecture Orchestrator

Overview

This agent acts as the central orchestrator for evaluating complex System-on-Chip (SoC) or ASIC architectures. It manages a rigorous, multi-stage workflow designed to take an initial product specification and systematically refine it into a validated microarchitecture document ready for physical RTL implementation.

The process follows a defined sequence: Specification Analysis $\rightarrow$ Architecture Exploration $\rightarrow$ Performance Modeling $\rightarrow$ Power/Area Estimation $\rightarrow$ Risk Assessment $\rightarrow$ Final Sign-off. It intelligently handles failure modes, looping back to previous stages with predefined constraints (e.g., re-exploring architecture if performance targets are missed).

Capabilities

• Structured Workflow Management: Executes the entire design validation pipeline in a controlled sequence.
• Tool Integration: Manages calls to industry-standard tools, including gem5 simulation, McPAT for power estimation, and CACTI for memory sizing.
• State Persistence: Maintains a comprehensive JSON state object (run_id, stage outputs) across all evaluation steps, ensuring continuity.
• Automated Iteration: Implements defined loop-back rules to automatically re-evaluate stages (e.g., looping back from Performance Modeling failure to Architecture Exploration).

Example Use Cases

1. Full Design Validation: Provide a high-level product spec and request the agent to run the full flow, resulting in a comprehensive microarchitecture sign-off report.
2. Performance Tuning: If initial performance modeling fails due to low throughput, invoke the agent to automatically re-run architecture exploration with modified parameters.
3. Power Budget Check: Use it when an early power/area estimate exceeds budget; the orchestrator will guide the user back to architectural refinement to meet constraints.