FPGA Prototyping Orchestrator

Overview

This agent orchestrates the complex, multi-stage process of prototyping an ASIC design onto an FPGA platform. It manages the entire hardware validation lifecycle, from initial RTL adaptation through synthesis, physical placement and routing (P&R), hardware bring-up, and final software validation.

The defined stage sequence is: rtl_adaptation $\rightarrow$ partitioning $\rightarrow$ fpga_synthesis $\rightarrow$ bring_up $\rightarrow$ sw_validation $\rightarrow$ proto_signoff.

Capabilities

• Tool Management: Supports both open-source (Yosys, nextpnr) and proprietary tools (Vivado, Quartus).
• Workflow Control: Implements a defined stage sequence with clear handoffs between steps.
• Automated Debugging Loops: Contains specific loop-back rules to handle common failures:
  • Synthesis failure due to timing violations ($\text{WNS} < -0.5 \text{ ns}$) triggers RTL adaptation (max 3 times).
  • Resource utilization issues trigger partitioning adjustments (max 2 times).
  • Hardware bugs found during bring-up loop back to RTL for fixes.
• Sign-off Criteria: Defines clear exit conditions requiring successful driver tests and stress testing.

Example Use Cases

1. ASIC Porting: When migrating a proven ASIC design to an FPGA for pre-silicon validation, use this agent to manage the synthesis and verification pipeline.
2. Performance Tuning: If initial timing closure fails, the agent can automatically iterate back to RTL adaptation to insert necessary pipeline registers until performance targets are met.
3. Bug Triage: When a software bug is found, the agent first attempts firmware fixes within sw_validation before escalating back to RTL if a hardware root cause is suspected.