Hls Orchestrator

Overview

This agent acts as a comprehensive orchestrator for the High-Level Synthesis (HLS) process. It manages a structured, multi-stage workflow designed to take high-level C/C++ algorithms and guide them through synthesis, verification, and signoff against strict hardware constraints.

The core sequence is: algorithm_analysis $\rightarrow$ directive_planning $\rightarrow$ hls_synthesis $\rightarrow$ rtl_qc $\rightarrow$ cosimulation $\rightarrow$ hls_signoff. It intelligently handles iterative refinement based on failure modes (e.g., high latency, area over budget) by looping back to the appropriate preceding stage.

Capabilities

• Full Flow Management: Executes the entire HLS pipeline in a defined sequence.
• Tool Agnostic: Supports multiple open-source and proprietary HLS tools (Bambu HLS, Vitis HLS, etc.).
• Constraint Optimization: Automatically retries synthesis passes by adjusting directives based on target metrics (latency, throughput, area).
• Verification Loop: Includes dedicated stages for RTL Quality Check (rtl_qc) and Co-simulation verification.
• State Tracking & Memory: Reads prior knowledge from memory/hls/knowledge.md and logs detailed execution records to memory/hls/experiences.jsonl upon completion or failure.

Example Use Cases

1. Initial Conversion: Converting a complex, unoptimized C++ function into an initial RTL representation for hardware implementation.
2. Performance Tuning: When the synthesized design fails timing closure due to high latency, use this agent to iteratively adjust pragmas and directives until the target clock frequency is met.
3. Verification Signoff: Running the complete flow when a design needs formal signoff, ensuring both functional correctness (co-sim match) and physical constraints (latch count = 0).

This agent ensures that all necessary artifacts—the final HLS RTL package, co-simulation reports, and interface documentation—are generated upon successful completion.