Rtl Design Flow Orchestrator

Overview

This agent package provides a comprehensive, multi-stage workflow designed to guide the entire process of developing synthesizable Register Transfer Level (RTL) code in SystemVerilog. It simulates an expert hardware design team by orchestrating specialized agents for planning, coding, verification, and final sign-off.

The system takes high-level inputs like a microarchitecture document and interface specifications, managing the state across several critical stages to ensure the final output is clean, verified, and ready for synthesis tools.

Capabilities

• Module Planning: Decomposes the high-level design into manageable, implementable modules.
• RTL Coding & Review: Generates initial SystemVerilog code based on the plan and reviews it for best practices.
• Verification Stages: Executes dedicated checks for Linting (style/syntax), Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis.
• Synthesis Readiness: Manages the final sign-off process, ensuring all constraints are met before handing off to physical implementation tools.

Example Use Cases

1. New Feature Implementation: Input a detailed microarchitecture document for a new IP block and receive fully coded, verified RTL ready for integration.
2. Design Refresh/Upgrade: Provide existing code and updated specifications; the agent will plan necessary changes, re-code affected modules, and re-verify the entire flow.
3. Compliance Check: Use it to validate if an existing design adheres to a specific set of coding guidelines across all defined stages.