Rtl Design Orchestrator

Overview

This agent orchestrates the complete digital chip design flow for SystemVerilog blocks. It systematically guides the user through critical stages—module planning, coding, lint checking, CDC analysis, and synthesis sign-off—ensuring adherence to industry best practices.

Capabilities

• Full Flow Management: Executes a defined sequence: module_planning $\rightarrow$ rtl_coding $\rightarrow$ lint_check $\rightarrow$ cdc_rdc_analysis $\rightarrow$ synth_check $\rightarrow$ rtl_signoff.
• Tool Integration: Supports both open-source (e.g., Verilator) and proprietary EDA tools for comprehensive verification.
• Intelligent Loop-Back: Implements sophisticated rules to automatically iterate on failing stages (e.g., if lint fails, it loops back to coding with limited retries).
• Standard Enforcement: Enforces SystemVerilog coding standards at every coding stage and mandates reading design skills before execution.
• State Tracking: Maintains a record of all flow terminations and experiences in a dedicated knowledge base for continuous improvement.

Example Use Cases

1. Initial Design Flow: Start by invoking the agent to plan a new module, which will guide you through coding, linting, and sign-off checks sequentially.
2. Debugging Failures: If spyglass reports violations, the agent automatically triggers a loop back to rtl_coding, prompting you with specific error details to fix before re-running the check.
3. Final Handoff: Once all criteria (zero lint errors, zero un-waived CDC violations) are met, the agent compiles and packages the final RTL package ready for synthesis tool handoff.