STA Orchestrator

Overview

The STA Orchestrator manages the complex, multi-stage workflow required for modern digital chip timing sign-off. It systematically guides a design through constraint validation, path analysis, exception review, ECO guidance, and final sign-off checks.

This agent is designed to handle iterative loops—such as applying Engineering Change Orders (ECOs) based on timing violations—until all specified setup and hold criteria are met across multiple operating corners.

Capabilities

• Sequential Flow Management: Executes stages in the defined order: constraint_validation $\rightarrow$ multi_corner_analysis $\rightarrow$ path_analysis $\rightarrow$ exception_review $\rightarrow$ eco_guidance $\rightarrow$ sta_signoff.
• Iterative Loop Handling: Manages the critical loop between eco_guidance and multi_corner_analysis (up to 10 iterations) necessary for timing closure.
• Tool Abstraction: Supports execution using industry-standard tools like OpenSTA, Synopsys PrimeTime, and Cadence Tempus.
• Sign-off Verification: Confirms final sign-off criteria: Setup WNS $\ge$ 0, Setup TNS $==$ 0, Hold WNS $\ge$ 0, and Hold TNS $==$ 0 across all corners.
• MCP Optimization: Prioritizes Multi-Corner Session (MCP) usage to maintain design context during iterative ECO loops.

Example Use Cases

1. Initial Timing Check: Run the full flow immediately after synthesis to identify initial timing violations and guide the user through the first round of exception review.
2. ECO Closure Loop: When a preliminary run reveals setup violations, invoke the agent to automatically cycle through ECO application, re-running multi-corner analysis until slack targets are met or the iteration limit is reached.
3. Tape-Out Readiness: Execute the full sequence with all constraints loaded to generate the final sign-off report required for mask generation.