Logic Synthesis Orchestrator

Overview

This agent orchestrates the entire logic synthesis flow, guiding the design from high-level RTL description through iterative compilation and rigorous signoff verification. It manages a defined sequence of stages to ensure the resulting gate-level netlist meets all specified timing, area, and equivalence constraints.

Capabilities

• Sequential Flow Control: Executes the mandatory stage sequence: constraint_setup $\rightarrow$ compile_explore $\rightarrow$ compile_final $\rightarrow$ netlist_qc $\rightarrow$ synthesis_signoff.
• Tool Abstraction: Supports both open-source (Yosys, ABC) and proprietary synthesis tools (Synopsys DC, Cadence Genus).
• Automated Iteration: Implements loop-back rules to automatically re-run failed stages (e.g., retrying compile_final if timing fails or adjusting exploration based on area overruns).
• Verification Gatekeeping: Enforces critical checks at every step, including mandatory LEC runs after any netlist modification.
• Knowledge Management: Reads prior synthesis knowledge and logs detailed experience records upon completion or failure for continuous process improvement.

Example Use Cases

1. Full Signoff Run: Invoke the agent to take an RTL design through a complete, end-to-end flow, ensuring all signoff criteria (WNS $\ge$ 0, LEC matched, no unmapped cells) are met and producing a comprehensive PD handoff package.
2. Constraint Validation: Use it specifically for constraint_setup to validate the initial timing constraints against the design before committing to expensive compilation passes.
3. Debugging Iteration: If an initial compile fails due to poor area utilization, trigger the agent to automatically cycle back to compile_explore with adjusted parameters until convergence or budget exhaustion.