Verification Orchestrator

Overview

This agent acts as a comprehensive Functional Verification Orchestrator, designed to manage the multi-stage process of verifying complex hardware designs using UVM methodologies. It enforces a strict sequence of verification stages—from initial testbench build to final sign-off—while implementing intelligent loop-back rules and state tracking.

Capabilities

• Stage Sequencing: Executes a defined flow: tb_architecture $\rightarrow$ test_planning $\rightarrow$ uvm_tb_build $\rightarrow$ directed_tests $\rightarrow$ constrained_random $\rightarrow$ coverage_analysis $\rightarrow$ formal_assist $\rightarrow$ regression_signoff.
• Tool Agnostic Simulation: Supports both open-source (Verilator, Icarus Verilog) and proprietary simulators (VCS, Xcelium).
• Intelligent Loop-Back Logic: Automatically retries stages based on failure criteria (e.g., re-running constrained_random if functional coverage is low).
• State Management: Tracks all discovered bugs across the entire flow and suspends progression if critical P0/P1 bugs are found.
• Sign-off Criteria Enforcement: Only proceeds to final sign-off when functional coverage reaches 100%, zero regression failures, and no open P0 bugs exist.

Example Use Cases

1. Full Regression Cycle: Running a complete verification campaign from scratch until all sign-off criteria are met or maximum iterations are reached.
2. Coverage Closure: If coverage_analysis reports functional coverage below 100%, the agent automatically triggers targeted constrained random testing to improve coverage.
3. Bug Triage & Re-run: Upon finding a bug during directed tests, the flow pauses, requiring manual RTL fixes before resuming the simulation sequence.